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DE2_lab_exercises
- 这是台湾友晶科技为DE2 FPGA开发板所提供的学习资料，非常适合大学数字电路的学习以及FPGA入门的人学习。-This is the Friends of the crystal technology DE2 FPGA development board provides learning materials, is ideal for university study and FPGA digital circuit who started learning.
DE2_user_manual_cn.pdf
- altera de2中文手册:de2提供了实用altera cyclone 2开发高级数字产品需要的所有模块.此为对应用户指南,在30分钟里面,可以浏览许多参考设计.-de2 user manual
4945579081DCT_2D
- dct-20 verilog vhdl de2
DE2_lab_exercises
- Altera DE2 原装光盘附带 案例教程 手把手教 十个实验 verilog hdl/vhdl-DE2_labs_ exercise with verilog/vhdl
hmm
- 此代码是在DE2平台上实现汉明码的编码和译码，包括简易的通信信道。-hanming code encode decode
Lab3
- Display text to the LCD of a DE2 board
music
- 以vhdl 語言利用nios編寫的音樂控制範例.altera de2板實測可用-Vhdl language used to write the music control nios sample. Altera de2 board can be measured
dianti1
- 该程序是一个简单的电梯控制程序,运用VHDL语言编程,能实现电梯所要的功能并在DE2板上演示-The program is a simple elevator control procedures, the use of VHDL language programming, to achieve the desired function of the elevator and in the DE2 board demo
T_PCNN1
- 关于pcnn图像分割的VHDL语言编写的程序,使用的是DE2板子-segmentation based on PCNN was implemented by FPGA
de2_70_air_hockey_game
- Verilog/VHDL project that implements a Air-Hockey game using a DE2-70 board and a LTM touch panel.
dtc
- 用DE2 开发板 来模拟仿真现实中的电梯控制 此程序中的电梯数目位8层-With the DE2 board to reality simulation of the elevator control this process the number of bits in the elevator 8 layer
DE2_115_CAMERA
- d5m的DE2驱动Verilog HDL -d5m driven on DE2 by Verilog HDL
uart_lcd1602
- 点亮altera公司DE2代开发板的1602液晶，采用niosII方法。-Light the LCD1602 of the altera DE2 board with the niosII method
LCD-controller---VHDL
- vhdl languge, i use the vhdl language for lcd controller with de2 board.
DE2_70_D5M1
- fpga，vhdl，de2-70，数字摄像头-fpga, vhdl, de2-70, a digital camera
PLL_1
- Phase lock loop generation for vhdl (DE2 board)
HanoiTower
- 使用Verilog HDL 以及VHDL语言，运用FPGA中的VGA显示原理以及键盘控制原理，开发汉诺塔简易游戏(The use of Verilog HDL and VHDL language, the use of FPGA in the VGA display principle and keyboard control principle, the development of Hanoi simple game)
clock
- there's a clock divider for DE2 altra board clock (50MHz)
de1_build
- The codes in the book are targeted for the DE1 board. Minor modifications are needed for the DE2 board. This directory contains the modified codes. Detailed use is explained in the pdf file within the directory.
de2_build
- De2_build: It contains the FPGA configuration file of the comprehensive Nios II system in Section 16.10.2 and software image files for the DE2 board. These files can be used for quick demo or software development. Note that the files can only be us